1. Field of the Invention
The present invention relates to a fabrication method for a metal oxide semiconductor (MOS) device comprising a double diffused drain (DDD). More particularly, the present invention relates to a fabrication method for an electrostatic discharge (ESD) protective circuit in a stacked dynamic random access memory (DRAM) device, in which the ESD protection circuit comprises a double diffused drain metal-oxide semiconductor device.
2. Description of the Related Art
During the fabrication of an integrated circuit, such as a dynamic random access memory device or a static random access memory (SRAM) device, or upon the completion of wafer fabrication, static electricity is one of most destructive factors that may induce damage in the integrated circuit. An electrical static discharge (ESD) protection circuit is therefore designed in the wafer to protect the wafer from damage due to external static electricity. Electrostatic damage often occur when a human body comes in contact with an electronic component, generating a high voltage surge, which causes serious damage to the electronic devices. For example, a human body walking on a carpet in a high humidity environment carries an electrostatic charge of about several hundred to about several thousand volts. The electrostatic charge can even exceed ten thousand volts in a low humidity environment. When an electrostatic charge carrier makes contact with a wafer, the electricity is released to the wafer and causes destruction of the wafer.
In the current design of an integrated circuit, the metal oxide semiconductor (MOS) in the integrated circuit comprising a lightly doped drain (LDD) is normally employed to prevent the generation of the hot carrier effect when the device dimensions are being reduced. The lightly doped drain of the metal oxide semiconductor, when being used as an electrical static discharge protection circuit, however, cannot provide the metal oxide semiconductor with sufficient protection from electrostatic discharge. The reason is summarized in the following.
FIG. 1 is a schematic, cross-sectional view of a metal oxide semiconductor comprising a lightly doped source/drain region. Referring to FIG. 1, the source/drain region 12 of the metal oxide semiconductor 10 comprises a lightly doped source/drain region 14. Since the dopant concentration in the lightly doped source/drain region 14 is lower, the electric field in the lightly doped source/drain region 14 is also weaker. As a result, the hot carrier effect generated at the channel 16 area is prevented when the dimensions of the metal oxide semiconductor are reduced.
Protection from electrostatic discharge, however, requires a higher electric field to discharge the high voltage static electrical charge. The metal oxide semiconductor comprising the lightly doped source/drain region mentioned in the above is inadequate for providing protection for an electrostatic discharge because the electric field at the lightly doped source/drain region is too weak.